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CUSTOMER APPROVAL SHEET
Company Name
MODEL
CUSTOMER
APPROVED
Name :
□
APPROVAL FOR SPECIFICATIONS ONLY (Spec. Ver.
□
APPROVAL FOR SPECIFICATIONS AND ES SAMPLE (Spec. Ver.
)
□
APPROVAL FOR SPECIFICATIONS AND CS SAMPLE (Spec. Ver.
)
□
CUSTOMER REMARK :
AUO PM :
P/N :
Title :
Comment :
)
Doc . v ers io n :
Tota l pa g es :
Da te
:
0. 5
28
20 0 8/ 11 / 05
Product Specification
7.0" COLOR TFT-LCD MODULE
MODEL NAME: A070VW04 V0
(PART NUMBER: 97.07A13.030)
< ◆ >Preliminary Specification
<
>Final Specification
Note: The content of this
specification is subject to change .
© 2006 AU Optronics
All Rights Reserved,
Do Not Copy.
Version:
0.5
Page:
1/28
Record of Revision
Version Revise Date
0
2007/11/09
0.1
2007/12/14
0.2
2008/01/10
Page
Content
Draft.
25
Modify the outline to “Reliability Test Ttem”
10,
Modify LED driving condition
26
Update Packing Form.
23
And Optical Spec.
0.3
2008/04/28
0.4
2008/07/22
11
Modify the figure of input timing details
0.5
2008/11/05
5
Modify the outline drawing
27
28
Update Recommend Gamma Voltage & Resistor
Add Suggestion- System block
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED,
OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Version:
0.5
Page:
2/28
Contents
A.
General Description ........................................................................................................ 3
C.
General Information ........................................................................................................ 4
B.
D.
Features ........................................................................................................................... 3
Outline Dimension........................................................................................................... 5
1. TFT-LCD Module – Front View ...................................................................................................................5
E.
2. TFT-LCD Module – Rear View.....................................................................................................................6
Electrical Specifications ................................................................................................. 7
1. FPC Pin Assignment
F.
(HRS FH28-60S-0.5SH).........................................................................................7
2 Absolute Maximum Ratings ........................................................................................................................9
Electrical Characteristics.............................................................................................. 10
1 TFT- LCD Typical Operation Condition (AGND = AGND2 = GND = GGND = 0V) ..................................10
2. Backlight Driving Conditions ...................................................................................................................10
3. AC Characteristics ....................................................................................................................................11
4. RGB Parallel Input Timing ........................................................................................................................11
5. Serial Control Interface AC Characteristic..............................................................................................13
6. Register Information .................................................................................................................................14
7. Register Table (Default Value) ..................................................................................................................15
8. Register Description .................................................................................................................................15
9. Recommended Power On Register Setting ............................................................................................18
10. Application Circuit Example...................................................................................................................19
G.
H.
I.
J.
K.
11. Recommended Power On/Off Sequence...............................................................................................21
Optical specification (Note 1, 2) ................................................................................ 23
Reliability test items(Note 2) ........................................................................................ 25
Packing Form................................................................................................................. 26
Recommend Gamma Voltage & Resistor (Gamma 2.2).............................................. 27
Suggestion- System block............................................................................................ 28
Version:
0.5
Page:
3/28
A. General Description
A070VW04 is a amorphous transmissive type TFT (Thin Film Transistor) LCD (Liquid crystal Display). This
model is composed of TFT-LCD, drive IC, FPC (flexible printed circuit), and backlight unit.The timing
controller is embedded, so it is easily to design for consumer product.
B. Features
7-inch display size
WVGA resolution and stripe dot arrangement
Built in timing controller
LED backlight
Standby mode supported
Up/Down, Left/Right reversion selection
SYNC + DE Mode
Parallel 18/24bits interface support
16 M color supported
Wide viewing angle
RoHS compliant green design
C. General Information
NO.
mm
152.40(H)×91.44(V)
mm
0.1905(H)×0.1905(V)
--
16.7M Colors
Screen Size
inch
dot
5
Color Configuration
--
7
Overall Dimension
9
Panel surface treatment
Pixel Pitch
Color Depth
8
Weight
10
4/28
Active Area
3
6
Page:
Unit
Display Resolution
4
0.5
Item
1
2
Version:
Remark
800RGB(H)×480(V)
7.0(Diagonal)
R. G. B. Stripe
Note 1
mm
164(H) × 103(V) × 5.1(T)
Note 3
--
Anti-Glare
g
Display Mode
Specification
--
Note 1: Below figure shows dot stripe arrangement.
Note 2
153.5 +/- 10%
Normally White
…………………………
…….
…….
(1
2
(1……………………..480)
…………
…
…
…
…………………………
3…………………………….2398 2399 2400)
Note 2: The full color display depends on 24-bit data signal
(pin 4~27).
Note 3: Not include blacklight cable and FPC. Refer next page to get further information.
5/28
Page:
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS
WITHOUT PERMISSION FROM AU OPTRONICS CORP.
1. TFT-LCD Module – Front View
D. Outline Dimension
0.5
Version:
6/28
Page:
2. TFT-LCD Module – Rear View
0.5
Version:
Version:
0.5
Page:
7/28
E. Electrical Specifications
1. FPC Pin Assignment (HRS FH28-60S-0.5SH)
Pin no
Symbol
I/O
2
AVDD2
P
1
3
4
5
6
7
8
9
AGND2
P
Analog Ground
VDD
P
Digital Power
R1
I
R0
R2
R3
R4
R5
Analog Power
I
Data input (LSB)
I
Data input
I
I
I
Data input
Data input
Data input
Data input
10
R6
I
Data input
12
G0
I
Data input (LSB)
14
G2
I
Data input
11
13
15
16
17
18
19
20
21
22
23
24
25
26
27
R7
G1
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Data input (MSB)
Data input
Data input
Data input
Data input
Data input
Data input (MSB)
Data input (LSB)
Data input
Data input
Data input
Data input
Data input
Data input
Data input (MSB)
28
DCLK
I
Clock input
30
HSYNC
I
Horizontal sync input. Negative polarity
32
SCL
I
Serial communication clock input
CSB
I
Serial communication chip select
29
31
DE
VSYNC
33
SDA
35
NC
34
I
I
I
--
Data enable signal
Vertical sync input. Negative polarity
Serial communication data input
Not connect (Please leave it open)
36
VDD
38
GND
37
P
--
Not connect (Please leave it open)
39
AGND1
P
Analog ground
41
VCOMin
43
NC
40
42
AVDD1
P
I
For external VCOM DC input (Optional)
Not connect
44
VCOM
O
connect a capacitor
46
V9
P
47
48
49
50
51
52
53
54
55
56
V10
V8
V7
V6
V5
V4
V3
V2
V1
NC
VGH
Not connect
P
Gamma correction voltage reference
P
P
P
P
P
P
P
P
-
Not connect
P
Positive power for TFT
57
GVCC
P
Digital Power
59
GGND
P
Digital Ground
58
60
VGL
CAP
P
C
8/28
Analog Power
-
45
Page:
Digital ground
NC
-
0.5
Digital Power
NC
P
Version:
Negative power for TFT
Connected to a capacitor
I: Input pin; P: Power pin; G: Ground pin; C: capacitor pin
2 Absolute Maximum Ratings
Item
Symbol
Condition
AVDD 1
AGND1=0
VCC
Power voltage
AVDD 2
VGH
VGL
Input Signal
Voltage
Operating
temperature
Storage
temperature
VGH-VGL
GND=0
AGND2=0
GGND = 0
VI
Version:
0.5
Page:
9/28
Min.
Max.
Unit
Remark
-0.5
15
V
Note 1
-0.3
40
V
Note 1
-0.5
5
V
Note 1
-20
0.3
V
Note 1
-0.3
VCC+0.3
V
Note 1
--
40
V
Topa
--
0
60
℃
Tstg
--
-10
70
℃
Note 1
Ambient
Temperature
Ambient
Temperature
Note 1: Functional operation should be restricted under normal ambient temperature.
Version:
0.5
Page:
10/28
F. Electrical Characteristics
The following items are measured under stable condition and suggested application circuit.
1 TFT- LCD Typical Operation Condition (AGND = AGND2 = GND = GGND = 0V)
ITEM
Symbol
MIN.
TYP.
MAX.
UNIT
Remark
VDD
3.1
3.3
3.6
20
V
mA
Note3
Pin3 + Pin36
10.5
11
11.5
V
Note3
IAVDD
--
10
20
mA
GVCC
3.1
3.3
3.6
V
Pin2 + Pin40
IGVCC
--
0.08
0.15
mA
--
0.35
0.5
mA
--
0.35
0.5
mA
GND
-
-
0.3VCC
AVDD – 1
V
-
AVDD/2
V
IVDD
AVDD 1
AVDD 2
Power supply
Signal
17.5
VGL
-7.5
VIH
0.7VCC
V1 ~ V5
AVDD/2
V6 ~ V10
1
IVGL
H Level
L Level
Input Reference
Voltage
VCOM
15
VGH
IVGH
Input
--
VIL
VCDC
18
3.3
18.5
-7
-6.5
-
VCC
3.6
Note3
Pin57
V
Note3
V
Note3
Pin56
Pin58
V
3.9
V
V
Note 1
Note1: Above every operation range is based on stable operation from suggested application circuit.
Note2: Based on recommended Gamma 2.2 voltage.
Note3: Typical current test pattern
2. Backlight Driving Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Remark
LED light bar Voltage
VL
---
12
12.5
V
---
LED lightbar Current
LED Life Time
IL
LL
120
10,000
140
---
160
---
mA
Hr
---
Note 2, 3
Note 1: The LED driving condition is defined for LED module (21 LED). The current range will be 120mA
to 160mA based on suggested driving voltage set as 12V.
Version:
0.5
Page:
11/28
Note 2: Define “LED Lifetime”: brightness is decreased to 50% of the initial value. LED Lifetime is
restricted under normal condition, ambient temperature = 25℃ and LED lightbar voltage = 12V.
Note 3: If it uses larger LED lightbar voltage more than 12V, it maybe decreases the LED lifetime.
3. AC Characteristics
PARAMETER
Clock High time
SYMBOL
TWCL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
8
-
-
ns
Clock Low time
TWCH
8
-
-
ns
Clock rising time
TRCLK
-
-
1
ns
Clock falling time
TACK
-
-
1
ns
Hsync setup time
THSU
5
ns
Hsync hold time
THHD
10
ns
Vsync setup time
TVSU
0
ns
Vsync hold time
TVHD
2
ns
Data setup time
TDSU
5
ns
Data hold time
TDHD
10
ns
Data enable set-up time
TESU
4
ns
Data enable hold time
TEHD
2
ns
Figure 1 : Input timing details
4. RGB Parallel Input Timing
a. Horizontal Timing
PARAMETER
DCLK frequency
SYMBOL CONDITIONS
FDCLK
MIN.
TYP.
MAX
UNIT
25
33
40
MHz
PARAMETER
SYMBOL CONDITIONS
DCLK period
Version:
0.5
Page:
12/28
MIN.
TYP.
MAX
UNIT
TDCLK
25
30.3
40
ns
Hsync Period (= THD + THBL)
TH
986
1056
1183
DCLK
Active Area
THD
-
800
-
DCLK
THBL
186
256
383
CLK
40
-
CLK
146
216
343
DCLK
Horizontal blanking (= THF +
THE)
Hsync front porch
THF
Delay from Hsync to 1 data input
st
Function of
THE
(= THW + THB)
HDL[5..0] settings
Hsync pulse width
THW
1
128
136
CLK
Hsync back porch
THB
10
88
342
CLK
MIN.
TYP.
MAX.
UNIT
497
505
512
Th
b. Vertical Timing
PARAMETER
SYMBOL CONDITIONS
Vsync period (= TVD + TVBL)
TV
Active lines
TVD
Vertical blanking (= TVF +
TVE)
480
TVBL
Vsync front porch
17
25
32
Th
1
-
Th
16
24
31
HS
TVF
TVE
GD start pulse delay
Function of
VDL[3..0] settings
Th
Vsync pulse width
TVW
1
3
16
Th
Hsync/ Vsync phase shift
TVPD
2
320
-
CLK
TH
HS
THF
T HW
T HB
DCLK
THE
R[7:0]
Rn-1
Rn
Invalid
R0
R1
R2
R3
Rn-1
Rn
Invalid
G[7:0]
Gn-1
Gn
Invalid
G0
G1
G2
G3
Gn-1
Gn
Invalid
B[7:0]
Bn-1
Bn
Invalid
B0
B1
B2
B3
Bn-1
Bn
Invalid
THBL
THD
Figure 2
Horizontal input timing. (HV mode)
THBL
Version:
0.5
Page:
13/28
THD
DE
DCLK
R[7:0]
Rn-1
Rn
Invalid
R0
R1
R2
R3
Rn-1
Rn
Invalid
G[7:0]
Gn-1
Gn
Invalid
G0
G1
G2
G3
Gn-1
Gn
Invalid
B[7:0]
Bn-1
Bn
Invalid
B0
B1
B2
B3
Bn-1
Bn
Invalid
Figure 3: Horizontal input timing. (DE mode)
TV
Vs
TVF
TVW
TVF
TH
Hs
TVE
Line
Xn-1
Xn
X1
X2
X3
Xn-1
TVBL
Xn
Invalid
TVD
Figure 4: Vertical timing. (HV mode)
DE
Line
Xn-1
Xn
X1
X2
X3
TVBL
Xn-1
Invalid
Xn
TVD
Figure 5: Vertical timing. (DE mode)
5. Serial Control Interface AC Characteristic
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
SCL pulse duty
TSCW
40
50
60
%
Serial data setup time
TIST
120
ns
Serial data hold time
TIHD
120
ns
Serial clock high/low
TSSW
120
ns
CSB setup time
TCST
120
ns
CSB hold time
TCHD
120
ns
Chip select distinguish
TCD
1
us
Delay from CSB to VSYNC
TCV
1
us
Serial clock
TSCK
CONDITIONS
320
ns
Version:
0.5
Page:
14/28
Vsync
30%
TCV
CSB
30%
30%
TCHD
TCST
SDA
70%
30%
D15
D14
TIST
SCL
70%
D13
TIHD TSSW
30%
D2
D1
TCD
D0
D15
D14
D13
D12
TSSW
TSCK
Figure 6 : AC serial interface write mode timing
6. Register Information
There is a total of 6 registers each containing several parameters. For a detailed description of the
parameters refer to register table.The serial register has read/write function. D[15:12] are the register
address, D[11] defines the read or write mode and D[10:0] are the data.
Figure 7: Serial interface write sequence
1. At power-on, the default values specified for each parameter are taken.
2. If less than 16-bit data are read during the CS low time period, the data is cancelled.
a.
The write operation is cancelled.
3. All items are set at the falling edge of the vertical sync, except R0[1:0].
4. When GRB is activated through the serial interface, all registers are cleared, except the GRB value.
5. The register setting values are valid when VCC already goes to high and after VSYNC starts.
6. It is suggested that VSYNC, HSYNC, DCLK always exists in the same time. But if HSYNC, DCLK stops,
only VSYNC operating, the register setting is still valid.
7. If the chip goes to standby mode, the register value will still keep. MCU can wake up the chip only by
changing standby mode value from low to high.
8. The register setting values are rewritten by the influence of static electricity, a noise, etc. to unsuitable value,
incorrect operating may occur. It is suggested that the SPI interface will setup as frequently as possible.
Version:
0.5
Page:
15/28
7. Register Table (Default Value)
ADDRESS
Reg
W
DATA
No. D15 D14 D13 D12 D11
D10
D9
D8
(01)
D7
R0
0
0
0
0
0
R1
0
0
0
1
0
X
R2
0
0
1
0
0
X
X
X
R3
0
0
1
1
0
X
X
(0)
(0)
R4
0
1
0
0
0
X
X
(0)
(0)
R6
0
1
1
0
0
X
0
(01)
D6
D5
D4
D3
D2
D1
D0
(1)
U/D
(0)
SHL
(1)
(1)
(0)
GRB
(1)
STB
(1)
VCOM_M
(01)
(01)
VCOM_LVL
(2Fh)
HDL(80h)
(0)
(0)
(00)
EnGB12 EnGB11 EnGB10
(1)
(1)
(1)
(0)
(0)
VDL(1000)
(1)
(1111)
(0)
EnGB5
(1)
EnGB4
(1)
EnGB3
(1)
(0)
X : Reserved, please set to “0”.
8. Register Description
R0 settings
Address
0000
Bit
[10..0]
Bits 10-9
Description
AUO Internal Use
Bits 8-7
AUO Internal Use
01
Bit5 (U/D)
Vertical shift direction selection.
0
Bit3
AUO Internal Use
1
Global reset.
1
Bit6
Bit4 (SHL)
Bit2
Bit1 (GRB)
Bit0 (STB)
AUO Internal Use
Horizontal shift direction selection.
AUO Internal Use
Standby mode setting.
Bit5
U/D function
1
Scan up; First line=G1 G2 … Gn-1 Last line=Gn.
Bit4
SHL function
1
Shift right: First data=Y1 Y2 … Y600 Last data=Y600. (default)
0
0
1
1
0
1
Scan down; First line=Gn Gn-1 … G2 Last line=G1. (default)
Shift left; First data=Y600 Y601 … Y2 Last data=Y1.
Bit1
GRB function
1
Normal operation. (default)
0
01
Default
The controller is reset. Reset all registers to default value.
Bit0
STB function
1
Normal operation. (default)
0
0001
0.5
Page:
16/28
T-CON, source driver and DC-DC converters are off, and all outputs are High-Z.
R1 settings
Address
Version:
Bit
[9..0]
Bit9-8
Bit7-6
(VCOM_M)
Bit5-0
(VCOM_LVL)
Description
Default
AUO Internal Use
01
VCOM mode signal.
01
VCOM level adjustment.
Step 31.25mV/LSB @AVDD=12.5V
(AVDD/400)
2Fh
Bit7-6
VCOM_M function.
01
VCOM internal reference disabled. DC voltage of VCOM follows VCOMin signal. (default)
00
VCOM generator disabled. VCOM is generated externally.
1x
VCOM generator enabled. DC voltage of VCOM follows VCOM_LVL settings.
Bit5-0
VCOM_LVL function @V1=12.5V
01h
VCOM_LVL = V1/2–46*31.25mV = 4.8125V
NOTE: Please refer to to Figure40.
00h
2Fh
VCOM_LVL = V1/2–47*31.25mV = 4.78125V
VCOM_LVL = V1/2 = 6.25V (default)
3Eh
3Fh
0010
Bit
[7..0]
Bit7-0 (HDL)
HDL function.
80h
THE = THEtyp. (default)
FFh
0011
Bit
[8..0]
Bit8
Bit7
TVE = TVEtyp – 7 Hs period.
0110
0111
1000
AUO Internal Use
0
0
0
1000
TVE = TVEtyp. (default)
TVE = TVEtyp + 3 Hs period.
1110
AUO Internal Use
0
1011
1101
AUO Internal Use
0
1100
80h
1001
1010
AUO Internal Use
Vertical start pulse adjustment function
0001
0101
Default
Bit3-0 (VDL)
VDL function.
0100
Description
Horizontal start pulse adjustment function
AUO Internal Use
Bit3-0
0011
Default
Bit5
Bit4
0010
Description
THE = THEtyp + 127 CLK period.
Bit6
0000
17/28
THE = THEtyp – 128 CLK period.
R3 settings
Address
Page:
VCOM_LVL = V1/2+16*31.25mV = 6.75V
Bit7-0
00h
0.5
VCOM_LVL = V1/2+15*31.25mV = 6.71875V
R2 settings
Address
Version:
1111
Version:
0.5
Page:
18/28
R6 settings
Address
0110
Bit
[9..0]
Description
Bit9
AUO Internal Use
Bit7(EnGB11)
Gamma buffer Enable for V8
Bit8(EnGB12)
Bit6(EnGB10)
Bit5
Bit4
1
1
1
AUO Internal Use
0
AUO Internal Use
0
Bit3(EnGB5)
1
Bit1(EnGB3)
1
Bit2(EnGB4)
Bit0
1
AUO Internal Use
Bitx
EnGBx function
1
Gamma buffer is enable. VX must be connected externally.
0
0
Default
0
Gamma buffer for VX is disable (High Z).
9. Recommended Power On Register Setting
ADDRESS
Reg
R/W
No. D15 D14 D13 D12 D11
DATA
D10
D9
D8
D7
01
R0
0
0
0
0
0
01
R1
0
0
0
1
0
0
R2
0
0
1
0
0
0
0
0
R3
0
0
1
1
0
0
0
0
0
R4
0
1
0
0
0
0
0
1
1
R6
0
1
1
0
0
0
0
1
1
01
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
1
1
0
01
2Fh
80h
0
0
00
1
0
0
1000
1
1111
0
1
1
(Note: for reference only, not limited to this circuit)
10. Application Circuit Example
R413
U401
CXLP100-100(10uH)
1
D404
3.3V
C416
2.2uF/35V/X5R/0805
1
2
19/28
C420
Page:
22nF/50V/X5R/0603
0.5
C
DAN217U
A
K
DM405
C414
Version:
1uF/35V/X5R/0603
3
3
R433
C415
0.1uF/25V/X5R/0603
C413
0.1uF/25V/X5R/0603
VGL
R422
C421
NO(RB551V-30)
0/5%/0603
D405
10nF/50V/X5R/0603
R419
1
2
3
4
5
6
7
8
10/1%/0603
R421
CT
SW
PGND
IN3
GH
IN2
GL
EN
16
15
14
13
12
11
10
9
C423
27pF/50V/X5R/0402
MP1530
/RDY
FB1
COMP
IN
GND
REF
FB2
FB3
56K/1%/0603 0/5%/0603
R420
R418
10K/1%/0603
C422
2.2uF/35V/X5R/0805
100K/5%/0603
FB_2
FB_3
FB_1
L402
CXLP100
R424
R426
10K/1%/0603
3
DM407
C
DM408
C
K
A
DAN217U
3
2
1
K
A
DAN217U
1
2
C
0/5%/0603
R432
DAN217U
A
K
DM406
C427
2.2uF/35V/X5R/0805
2
1
C430
22uF/16V/X5R/1206
0.1uF/25V/X5R/0603
C424
EN
0.1uF/25V/X5R/0603
C425
78K/1%/0603
0/5%/0603
R425
3
SB07-03C
R415
0.1uF/10V/X5R/0402
5.1k/1%/0603
R430
10/1%/0603
C429
0/5%/0603
2.2uF/25V/X5R/0805
C428
27pF/50V/X5R/0603
24K/1%/0603
R428
R429
110K/1%/0603
R427
261/5%/0603
AVDD
+11V
R431
5.1K/5%/0603
VGH
+18V
-7V
C418
R417
10K/1%/0603
R414
6.8K/5%/0603
C419
C417
0.1uF/25V/X5R/0603
R423
2
10uF/10V/X5R/0805
1
2
NO(0/5%/0603)
R412
C426
0/5%/0603
1uF/35V/X5R/0603
3.3V
R324
0/5%/0603
0/5%/0603
R323
4
3
-
+
1
U301A
0/5%/0603
R325
NO(AD8565)
AVDD
0.1uF/16V/X5R/K/0402
C323
AVDD
0.1uF/16V/X5R/0402
C301
C324
R301
R515
R312
R311
R310
R309
R308
R307
R306
R305
R304
R303
NO(10K/5%/0603)
R516
0/5%/0603
R302
1uF/16V/X5R/0603
1uF/16V/X5R/0603
C302
VCOM
VCOMin
V5
V4
V3
V2
V1
Page:
R322
R321
R320
R319
R318
R317
R316
R315
R314
R313
V10
V9
V8
V7
V6
20/28
0.5
3.3V
3.3V
AVDD
C506
DGND
AVDD
DGND
3.3V
VGL
VGH
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
VCOM
VCOMin
DGND
C505
1
2
3
R0
4
R1
5
R2
6
R3
7
R4
8
R5
9
R6
10
R7
11
G0
12
G1
13
G2
14
G3
15
G4
16
G5
17
G6
18
G7
19
B0
20
B1
21
B2
22
B3
23
B4
24
B5
25
B6
26
B7
27
DCLK 28
DE
29
HS
30
VS
31
SCL 32
SDA 33
CSB 34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AGND2
AVDD2
VDD
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
DCLK
DE
HSY NC
VSY NC
SCL
SDA
CSB
NC
VDD
NC
GND
AGND1
AVDD1
VCOMin
NC
NC
VCOM
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
NC
VGH
GVCC
VGL
GGND
CAP
CON60
VR301
EVM3RSX50B14
AVDD
2
5
10uF/16V/X5R/1206
10uF/10V/X5R/K/0805
C303
C304
C305
C306
C307
1uF/16V/X5R/0603
1uF/16V/X5R/0603
1uF/16V/X5R/0603
C308
C309
1uF/16V/X5R/0603
1uF/16V/X5R/0603
1uF/16V/X5R/0603
1uF/16V/X5R/0603
1uF/16V/X5R/0603
C310
C311
C322
VCOM
10uF/10V/X5R/K/0805
Version:
10uF/10V/X5R/K/0805
Version:
0.5
Page:
21/28
11. Recommended Power On/Off Sequence
Power On Sequence
Version:
0.5
Page:
22/28
Power Off Sequence
VCC
90%
VCC
0%
> 10us
90%
GND
VCC
Serial Interface
0%
GND
VCC
90%
Vsync
0%
GND
VCC
90%
Digital Input
0%
AVDD
90%
AVDD
0%
> 0us
100%
VGL
0%
GND
GND
GND
VGL
> 0us
VGH
90%
VGH
0%
>80ms
90%
GND
VLED
LED
0%
GND
G. Optical specification
Item
Response Time
Symbol
Rise
Fall
Contrast ratio
Viewing Angle
(Note 1, 2)
Condition
Tr
θ=0°
Tf
CR
At optimized
viewing angle
Top
CR≧10
Bottom
Left
Brightness
Right
White Chromaticity
Version:
0.5
Page:
23/28
Min.
Typ.
Max.
Unit
Remark
-
12
20
ms
Note 3
200
300
-
30
50
-
50
65
-
-
50
50
18
30
-
65
θ=0°
150
200
-
X
θ=0°
0.26
0.31
0.36
y
θ=0°
0.28
0.33
0.38
lightbar voltage VL = 12 V.
in the dark room.
To be measured
Note 4
-
65
YL
Note 1:Ambient temperature =25 ℃ , and LED
ms
deg.
Note 5
cd/m
Note 6
2
------------------------------
Note 2:To be measured on the center area of panel
with a viewing cone of 1° by Topcon
luminance meter BM-7, after 15 minutes
operation.
Note 3. Definition of response time:
The output signals of photo detector are measured when the input signals are changed from “black” to
“white”(falling time) and from “white” to “black”(rising time), respectively.
The response time is defined as the time interval between the 10% and 90% of amplitudes.
figure as below.
S i gnal ( R el at i ve val ue)
100%
90%
"Black"
"White"
10%
0%
Note 4.Definition of contrast ratio:
Tr
Refer to
"White"
Tf
Version:
0.5
Page:
24/28
Contrast ratio is calculated with the following formula.
Contrast ratio (CR)=
Photo detector output when LCD is at “White” state
Photo detector output when LCD is at “Black” state
Note 5. Definition of viewing angle, θ, Refer to figure as below.
Note 6. Measured at the center area of the panel when all the input terminals of LCD panel are electrically
opened.
Version:
0.5
Page:
25/28
H. Reliability test items(Note 2)
No.
Test items
1
High Temperature Storage
3
High Ttemperature Operation
5
High Temperature & High Humidity
6
Heat Shock
7
Electrostatic Discharge
2
4
Conditions
Ta= 70℃
Low Temperature Storage
Ta= -10℃
240Hrs
Low Temperature Operation
Ta= 0℃
240Hrs
Ta= 60℃
240Hrs
Ta= 50℃. 80% RH
-10℃~60℃, 50 cycle,
240Hrs
Operation
2Hrs/cycle
Non-operation
±200V,200pF(0Ω), once for each terminal
Frequency range
Stoke
8
240Hrs
Vibration
Sweep
: 8~33.3Hz
: 1.3mm
:2.9G ,33.3~400Hz
2 hours for each direction of X,Y,Z
4 hours for Y direction
9
Mechanical Shock
10
Vibration (With Carton)
11
Drop (With Carton)
Remark
100G . 6ms, ±X,±Y,±Z
3 times for each direction
Random vibration:
0.015G /Hz from 5~200Hz
2
–6dB/Octave from 200~500Hz
Non-operation
Non-operation
JIS C7021,
A-10
condition A
: 15 minutes
Non-operation
JIS C7021,
A-7
condition C
IEC 68-34
Height: 60cm
1 corner, 3 edges, 6 surfaces
Note 1: Ta: Ambient Temperature.
Note 2: In the standard conditions, there is not display function NG issue occurred. All the cosmetic
specification is judged before the reliability stress.
Version:
0.5
Page:
26/28
I. Packing Form
J.
Version:
0.5
Page:
27/28
Recommend Gamma Voltage & Resistor (Gamma 2.2)
Gamma 2.2
00H
10H
20H
30H
AVDD
V1
11
10
V2
8.7
V4
7.68
V6
4.2
V3
8.1
6.8
3FH
V5
30H
V7
3.32
V9
2.3
3FH
20H
10H
00H
V8
V10
2.9
1
Version:
0.5
Page:
28/28
K. Suggestion- System block

customer approval sheet customer approval sheet - Display

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