US2020 Device Specifications

(Preliminary)
US2020
136x160 Dots OEL Controller/Driver with 160-Level Gray Scales
1.0 General Description
US2020 is a monolithic IC that provides the control circuitry to drive OEL panel size up to 136 x
160 pixels. US2020 is able to display a graphics in maximum 160-level gray scale. US2020
connects to a host processor, and has an internal display SRAM (136x160x8 bits) where is used
to store bit-mapped data for the Organic Electro-Luminescent (OEL) panel. It reads data from
SRAM and automatically refreshes the OEL. It provides a simple interface to an eight bits host
data bus, providing all necessary address mapping in hardware.
ALU hardware provided on chip allows US2020 to perform pixel set, clear, and byte write. The
result is that drawing operations are fast and efficient. It allows custom hardware to be designed
to deal with OEL specific requirements of timing and addressing. In addition, these devices are
low power, fairly low cost, and easily modified.
2.0 Features
‹ Dot Matrix: 136 Scan x 160 Data
‹ Internal Display SRAM: 136 x 160 x 8-bit
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‹ Color Depth: 160-Level Gray Scales (Maximum)
‹ Interface: 8-bit Parallel with Address A[2:0] to Select Command & Parameter / Data
‹ 16 Steps Contrast / Pre-Charge Control
‹ Programmable Refresh Rate
‹ Row Re-Mapping & Column Re-Mapping
‹ Four Operation Modes: Edit, Video, Controller Power Down, Driver Power Down.
‹ Support 2-D Graphic Acceleration
‹ Support Dynamic Box Display
‹ Support Partial Display
‹ Power Down Management: Single External Pin to Control Power Down Mode On / Off
‹ On-Chip Oscillator with Multiple Frequency Select
‹ External Current Reference
‹ 20MHz Clock Frequency at VDD=2.1V ~ 4.4V
‹ Supply Voltage for OEL Driver: 3.3V ~ 18V
‹ Package: TCP, COF
3.0 Advantages
The advantages of US2020 over other OEL controllers are as follows:
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(Preliminary)
US2020
1) All address mapping is done in hardware. All OEL operations are done directly in terms of
H and V position. This saves many processor instructions involved in address calculations.
This is particularly true on the UV2020 OEL module because of its unconventional
eight-quadrant data format requirement.
2) Registers are directly mapped to the Host CPU bus. US2020 uses eight directly mapped
registers. This approach saves the Host CPU Cycles needed to write register addresses
to the chip prior to data.
3) Several useful drawing operations are implemented in hardware.
4) Drawing operations are fast: no handshake is required to ensure that a drawing operation is
complete before the next is initiated.
5) No software initialization is required: the OEL is fully functional upon power up. (Most OEL
controllers do not operate correctly until their registers are initialized. This delay can cause
damaging voltages to be applied to the OEL.)
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(Preliminary)
US2020
4.0 Block Diagram
Internal SRAM
Logic Symbol
R/W Enable
CS
Memory
Data
Memory
Address
MD[7:0]
MA[15:0]
Memory
/OE
Memory
/WE
/ROMOE
/RAMWE
RAM Interface
/WRITE
Host R/W
/CSOELCK
CS2
Host Chip Select
OELH
Host Data
IDB[7:0]
OELV
Host Address
AA[2:0]
RESETB
CKIN
OEL Control
UD[7:0]
OEL Data
RESET
Figure 1 : Connections to a Host CPU, Display RAM, and the OEL panel.
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Oscillator
OEL
TIMING
CKIN
HORIZ.
COUNTER
HORIZ.
TRANSLAT
VERTICAL
COUNTER
VERTICAL
TRANSLAT
OELCK
OELH
OELV
RESETB
OEL
DRIVER
MA[14:0]
MEMORY
ADDRESSING
HPOS.
REGISTER
VPOS.
REGISTER
OEL
DATA
SCAN
[136:1]
DATA
[160:1]
MD[7:0]
MEMORY
DATA
UD[7:0]
OEL DATA
HOST DATA
BUS IDB[7:0]
HOST
ADDRESS
AA[2:0]
/CS
/WT
CS2
RESET
READ
REGISTER
ADDRESS
DECODER
ALU
DATA
REGISTER
OPCODE
REGISTER
Figure 2 : Host CPU Block Diagram
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US2020
4.1 Functional Block Descriptions
Microprocessor Parallel 80-series Interface
The parallel interface consists of 8 bits data pins DBUS [7:0], 3 bits address pins AA [2:0], WTB,
CSB and CS2. WTB input High indicates a read operation from the status register. WTB input
Low indicates a write operation to Display Data RAM or Internal Command Registers. CSB
input serves as data and registers read/write strobe signal when low provided and CS2 is pulled
high respectively. Refer to Figure 3 of parallel timing characteristics for Parallel Interface Timing
Diagram.
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry.
for the Display Timing Generator.
The oscillator generates the clock
OEL Driving Current Control Block
This block is used to divide the incoming power sources into the different levels of internal use
voltage and current. BIASRES is a reference voltage, which is used to deliver a reference
current source for Data Cells current drivers.
Internal Display SRAM
The internal SRAM is a mapped buffer holding the pattern to be displayed. As the US2020 can
control a 136-scan x 160-data display with 7 bits of gray scale, the size of the SRAM is organized
as 136 x 160 x 8 bits = 21760 bytes.
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US2020
5.0 Pin Description
Pad
Name
SCAN [136]
︰
SCAN [1]
DATA [125]
DATA [123]
︰
DATA [3]
DATA [1]
DATA [2]
DATA [4]
︰
DATA [124]
DATA [126]
DATA [128]
DATA [130]
︰
DATA [158]
DATA [160]
DATA [159]
DATA [157]
︰
DATA [129]
DATA [127]
I/O
O
︰
O
O
O
︰
O
O
O
O
︰
O
O
O
O
︰
O
O
O
O
︰
O
O
73
93
VDD
I
69
91
GND
I
VDDHV
I
Power Supply for OEL Panel
GNDHV
I
Ground of OEL Panel
96
BIASRES
I
Current Mirror Bias Resistor
This pin is current reference pin. A resistor should be
connected between this pin and VDDHV.
66
97
GNDHV1
I
Ground of Current Mirror
241-376
1-63
100-162
224-240
Description
OEL Scan Output
These pins provide the OEL scan driving signals.
OEL Data Output
These pins provide the OEL data driving signals. The output
voltage level of these pins is in high impedance stage when
display is off.
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377-393
64
68
94
99
65
67
95
98
89
SELCKIN_EXT
I
92
CLOCK
I
Power Supply for Logic Circuit
It must be connected to external source.
Ground of Logic Circuit
A reference for the logic pins. It must be connected to
external ground.
Select Internal/External System Clock Source.
This pin is internal oscillator enable. When this pin is pull low,
internal oscillator is enabled. The internal oscillator will be
disabled when it is pulled high, an external oscillator source
must be connected to CLOCK pin for normal operation.
External System Clock Source.
This pin is the system oscillator input.
When internal
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Pad
Name
74
CTRL_PD
88
DRV_PD
90
RSTB
71
75
TEST1
TEST2
72
CS2
70
CSB
76
WTB
77-79
AA [0:2]
80-87
DBUS [0:7]
163-223
397-454
NC
US2020
I/O
Description
oscillator is enabled, this pin should be left open. Nothing
should be connected to this pin. When internal oscillator is
disabled, this pin receives display clock signal from external
oscillator source.
Controller Power Down.
I Logic 0 : controller working.
Logic 1 : controller power down, driver reset.
Driver Power Down
This pin will send out a signal that could be used to set
O
external DC/DC converter circuit enable/disable or other
applications.
Power Reset for Controller and Driver
When the pin is low,
I This pin is reset signal input.
initialization of the chip is executed.
Test
I These are reserved pins for IC testing. They must be
connected to ground for normal status.
Chip Select (Host Enable Select)
Chip select is used to access registers, this is driven from the
I microprocessor’s I/O enable signal ANDed with the address
selection logic. When this pin is pull high, then the functions
become active.
Chip Select (Read/Write Enable Strobe)
Chip select is used to access registers, this is driven from the
I microprocessor’s I/O enable signal ANDed with the address
selection logic. When this pin is pull low, then the functions
become active.
Read/Write Enable
This pin is used with CSB to access registers. The interface
I
is places in a read mode when a high pulse is entered and
placed in a write mode when a low pulse is entered.
Host Register Address Bus
I These pins are 3 bits internal registers selecting bus to be
connected to the microprocessor’s data bus.
Host Data Input/Output Bus
I/O These pins are 8 bits data bus to be connected to the
microprocessor’s data bus.
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-
Dummy Pads, No Connect
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US2020
(Preliminary)
6.0 Electrical Characteristics
6.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Characteristics
Symbol
Rating
Supply Voltage (Low Voltage)
Supply Voltage (High Voltage)
Input Voltage
Storage Temperature Range
VCC
VDDHV
VI
TSTO
-0.5 V to 7V
3.3 V to 18 V
-0.5 V to VCC +0.3V
-40 to +125°C
Characteristics
Symbol
Rating
Supply Voltage (Low Voltage)
VDD
2.1 V to 4.4V
Supply Voltage (High Voltage)
VDDHV
7.0 V to 18 V
Program Voltage
VPP
VDD
Operating Temperature Range
TOP
-20 to +70°C
6.2 Recommended Operating Conditions
6.3 DC Characteristics
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Characteristics
Symbol
Supply Voltage
VDD
Program Voltage
VPP
High Level Input
Conditions
Min
Typ
Max
Unit
2.1
3.3
4.4
V
Input Signal Supply
2.1
3.3
4.4
V
VIH
TTL inputs
2.0
-
VDD
V
Low Level Input
VIL
TTL inputs
VSS
-
0.8
V
High Level Output
VOH
IOH = 4mA DC
2.4
-
VDD
V
Low Level Output
VOL
IOL = 4mA DC
VSS
-
0.45
V
Standby Current
ISB
No Panel Attached
1
5
50
µA
Input Leakage
IIN
VI = VOL or GND
-10
-
10
µA
3-state Leakage
IOZ
VO = VDD or GND
-10
-
10
µA
VDD Supply Current
IDD
-
-
25
mA
Output Short Circuit
IOS
-
-
-100
mA
VO = 0V
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US2020
6.4 Access Timing
Symbol
Description
Min
tCS
Host cycle chip select pulse width
tDac
Host read data access time
75 nS
50 nS
tADsu
Host Address setup time
20 nS
tADh
Host cycle Address hold time
20 nS
tDRh
Host read cycle disable time
20 nS
tDWsu
Host write cycle data setup time
20 nS
tDWh
Host write cycle data hold time
20 nS
tCK
Max
CSIN clock cycle time (Data R/W)
6 clock cycle*
CSIN clock cycle time (Command R/W)
105 nS
*Note: For Example, if the driver clock = 10MHz, the min. tCK = 600nS.
should be the external or internal clock, after frequency divides.
And the driver clock
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AA [2:0]
CS2
WTB
tCK
tCS
CSB
tADsu
tADh
DBUS [7:0]
Write (WTB = 0)
Valid Data
tDWsu
tDWh
DBUS [7:0]
Read (WTB = 1)
Valid Data
tDac
tDRh
Figure 3 : Host read/write cycle timing
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US2020
7.0 Registers Descriptions
This section provides a detailed description of the US2020 control registers as shown in following
table. There are eight registers selected by address lines AA2, AA1, AA0. The display data
written to OEL panel has two modes, EDIT and VIDEO modes. In the EDIT mode, the pixel
position (horizontal and vertical locations) must be written before the pixel DATA (gray scales) is
written to the OEL controller. In VIDEO mode, A display window is set by (H1, V1) and (H2, V2)
in window diagonal edge position, and the pixel DATA writing sequence is start from H1 through
H2 on V1 row, then return to H1 of V1+1 row till reach to H2 of V2. No further pixel H and V
position is required to write to the US2020 controller. The display Data written to the controller
in VIDEO mode is at least three times faster than that in EDIT mode.
Register
Address
A[2:0]
0:000
1:001
2:010
3:011
4:100
5:101
6:110
7:111
Register
Name
HPANEL
HPOS
VPANEL
VPOS
DATA
OPCODE
CNTL
SETUP
DBUS [7:0]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UH7 UH6 UH5 UH4 UH3 UH2 UH1 UH0
H7
H6
H5
H4
H3
H2
H1
H0
UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0
V7
V6
V5
V4
V3
V2
V1
V0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
O2 O1 O0
R/W
W
W
W
W
R/W
W
W
W
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Register Function
OEL Panel Size in Horizontal Direction
Mnemonic
HPANEL
HPANEL register is used to define OEL panel size in H direction (Total number of Data
lines). A default of 160 Data lines is set in the controller using Bit 7 of CNTL.
HPANEL is active once CNTL Bit 7 is set to 1.
Register Function
Pixel Horizontal Position
Mnemonic
HPOS
The Horizontal Position Register (HPOS) forms an eight bits number, which is used to
specify the horizontal (Data) position of the pixel or byte to be accessed. US2020 is
available for 160 horizontal pixels. Valid OEL HPOS values are 0 through 159.
When writing pixel addresses in EDIT mode, HPOS must be written. This is because
writing HPOS is the action that causes pixel operations to occur. When writing pixel in
VIDEO mode, HPOS is used to define H1 and H2 pixel positions once with associated
OPCODE. HPOS is no need to be written in VIDEO mode once H1 and H2 are written.
The HPOS register is Write only. Reads to this register return indeterminate data.
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Register Function
OEL Panel Size in Vertical Direction
US2020
Mnemonic
VPANEL
VPANEL register is used to define OEL panel size in V direction (Total number of Scan
lines). A default of 136 Scan lines is set in the controller using Bit 7 of CNTL.
VPANEL is active once CNTL Bit 7 is set to 1.
Register Function
Pixel Vertical Position
Mnemonic
VPOS
The Vertical Position Register, VPOS, forms an eight bits number, which is used to
specify the vertical (Scan) position of the pixel or byte to be accessed. US2020 is
available for 136 vertical pixels. Valid OEL VPOS values are 0 through 135.
When writing pixel addresses in EDIT mode, VPOS must be written. This is because
writing VPOS is the action that causes pixel operations to occur. When writing pixel in
VIDEO mode, VPOS is used to define V1 and V2 pixel positions once with associated
OPCODE. VPOS is not needed to be written in VIDEO mode once V1 and V2 are
written. The VPOS register is Write only. Reads to this register return indeterminate
data.
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Register Function
Data Register
Mnemonic
DATA
The DATA Register is used to write bytes of data from the Display when byte
operations are used. The DATA register is also read the controller status from
controller to host. The display data can not be read from controller.
Register Function
Op Code Register
Mnemonic
OPCODE
There are two methods to write graphics to US2020: Pixel VIDEO and Byte drawing
operations. Within each method, there are several drawing modes. All modes are
set by writing a three bits opcode as shown in the following table to the OP register.
There are four operations for Pixel VIDEO mode and four Byte drawing operations.
The OPCODE register below is used as command set in VIDEO mode.
OPCODE (0, 0, 0) is used to set the H1 and V1 pixel positions.
OPCODE (0, 0, 1) is used to set the H2 and V2 pixel positions.
OPCODE (0, 1, 0) is used to start the loading of DATA bytes.
OPCODE (0, 1, 1) is used to end the loading of DATA bytes and VIDEO mode.
The followed OPCODE Register is used to select the drawing operation to be performed
in EDIT mode. The drawing operations can change the bit’s value in DATA byte during
the write status. The drawing operations include
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US2020
OPCODE (1, 0, 0) performs DATA byte OR operation.
OPCODE (1, 0, 1) performs DATA byte AND1B operation.
OPCODE (1, 1, 0) performs DATA byte XOR operation.
OPCODE (1, 1, 1) performs DATA byte write operation.
CODE
Opcode
000
001
010
011
100
101
110
111
SETH1V1
SETH2V2
STARTFRAME
STOPFRAME
ORBYTE
AND1BBYTE
XORBYTE
WRTBYTE
Function
Set H1 and V1 pixel position
Set H2 and V2 pixel position
Start the loading DATA bytes
Ending the loading DATA bytes
OR Byte of DATA with current display data
AND1B Byte of DATA with current display data
XOR Byte of DATA with current display data
WRITE Byte of DATA over current display data
Register Function
Controller Controls
Mnemonic
CNTL
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The Driver Power Control (CNTL [0])
This command turns the display On and Off. The register will send out a signal from the Pad
[88] DRV_PD. This function can use to set external DC/DC converter circuit enable/disable.
CNTL [0]
0
1
Driver Power
Off
On
Brightness Control through Gray Scale (CNTL [2:1])
This command supports adjusting brightness by manual.
Control through Frame Rate (CNTL [3]).
CNTL [2]
0
0
1
1
CNTL [1]
0
1
0
1
It could be used with Brightness
Brightness
Full
Half
1/4
1/8
Brightness Control through Frame Rate (CNTL [3])
The US2020 supports various frame scanning rates. It will influence the brightness and could
be used with Brightness Control through Gray Scale (CNTL [2:1]).
CNTL [3]
0
1
Brightness
Full
Half
The above two brightness controls can be used in combination!
Internal Oscillator Frequency Select Control (CNTL [4])
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US2020
The US2020 supports various internal oscillator frequency selections.
CNTL [4]
0
1
Frequency
10 MHz
20 MHz
Default Panel Size CNTL [7]
When CNTL [7] is 0, a default OEL panel of 160 Data lines and 136 Scan lines is defined in the
controller. When CNTL [7] is 1, this will allow the specified panel size can be input to the
controller. Use this option in cautious to avoid the damage of driver IC and OEL panel.
Register Function
Controller Initialization
Mnemonic
SETUP
The controller initialization is set by SETUP register.
follows:
Several functions are described as
Contrast Control (SETUP [3:0])
The contrast control is made through controlling the OEL pixel discharge time. A maximum of
16 clocks time SETUP [1, 1, 1, 1] is possible in the controller, a minimum of 1 clock time, SETUP
[0, 0, 0, 0] is used in the controller.
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Oscillator Frequency Selection (SETUP [5:4])
This command is a factor and must to use with Internal Oscillator Frequency Select Control
(CNTL [4]).
SETUP [5]
0
1
1
SETUP [4]
1
0
1
OSC Frequency (MHz)
Half
1/4.
1/8.
H, V Direction Selection (SETUP [7:6])
This command can select the output direction of scan lines and data lines. The V direction
(scan lines) can be reversed when SETUP [6] is set to 1. The H direction (data lines) can be
reversed when SETUP [7] is set to 1. It will decide the display start position from different
corner based on face up IC type.
SETUP [7]
SETUP [6]
0
0
0
1
1
0
1
1
12
Direction
V – Normal, H – Normal
Top left corner
V – Reverse, H – Normal
Top right corner
V – Normal, H – Reverse
Bottom left corner
V – Reverse, H – Reverse
Bottom right corner
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US2020
7.1 Command Table
Register Address –
AA [2:0]
000 (HPANEL)
001
(HPOS)
010 (VPANEL)
011
(VPOS)
100
(DATA)
101 (OPCODE)
Data – DBUS [7:0]
Function
D7
D7
D7
D7
D7
*
*
*
*
D6
D6
D6
D6
D6
*
*
*
*
D5
D5
D5
D5
D5
*
*
*
*
D4
D4
D4
D4
D4
*
*
*
*
D3
D3
D3
D3
D3
*
*
*
*
D2
D2
D2
D2
D2
0
0
0
0
D1
D1
D1
D1
D1
0
0
1
1
D0
D0
D0
D0
D0
0
1
0
1
*
*
*
*
*
1
0
0
*
*
*
*
*
1
0
1
*
*
*
*
*
1
1
0
*
*
*
*
*
1
1
1
*
*
*
*
*
*
*
*
*
*
0
1
*
*
*
*
0
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
1
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
0
1
*
*
*
1
0
1
*
*
*
*
OEL panel size in horizontal direction
Pixel vertical position
OEL panel size in horizontal Direction
Pixel vertical position
Data register
Set H1 and V1 pixel position
Set H2 and V2 pixel position
Start the loading DATA bytes
Ending the loading DATA bytes
OR Byte of DATA with current display
data
AND1B Byte of DATA with current
display data
XOR Byte of DATA with current
display data
WRITE Byte of DATA over current
display data
Driver power off
Driver power on
Brightness – Full
Brightness – Half
Brightness – 1/4
Brightness – 1/8
Frame rate – Full
Frame rate – Half
Internal oscillator frequency – 10 MHz
Internal oscillator frequency – 20 MHz
Default panel size
Specified panel size
Contrast control
Oscillator frequency factor – Half
Oscillator frequency factor – 1/4
Oscillator frequency factor – 1/8
Display start position – Top left
Display start position – Top right
Display start position – Bottom left
Display start position – Bottom right
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110
(CNTL)
111
(SETUP)
*
*
*
0
*
*
*
1
*
0
0
*
*
0
1
*
*
1
0
*
*
1
1
*
0
*
*
*
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D3 D2 D1 D0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
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US2020
7.1 Functional Specification
7.1.1 Commands
The US2020 identify the data bus signals by a combination of 8 bits data pins DBUS
[7:0], 3 bits address pins AA [2:0], WTB, CSB and CS2. In the explanations below the
commands are explained using the 80 series microprocessor interface as the example.
7.1.2 Actual application example
Command usage and explanation of an actual example.
1) Command entry procedures when turning on the power supply
Turn on the power supply (VDD, VDDHV)
↓
Be sure to execute power on resetting (RSTB=”1”)
↓
<Power setting 1>
Sleep out (CTRL_PD=”0”) *1
↓
<Initial setting 1>
Initial control
Chip select signal (CS2=”1”)
Chip enable (CSB=”1”)
Read/write control (WTB=”1”)
↓
Oscillation ON
Internal Oscillator Clock Setting (not necessary, when use external oscillator)
8MHz：CNTL[4]=”1”,
4MHz：CNTL[4]=”0”.
↓
Oscillator Frequency (SETUP[5:4])
↓
Panel size setting
Control panel size (CNTL[7]=”1”)
↓
Set HPANEL (AA [2:0]=”000”)
↓
Set VPANEL (AA [2:0]=”010”)
↓
Origin head-section setting (SETUP[7:6])
↓
Frame rate setting (CNTL[3])
↓
Contrast Control (SETUP[3:0])
↓
<Power setting 2>
Display ON (CNTL[0]=”1”)
↓
<Initial setting 2>
Brightness control (CNTL[2:1])
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US2020
*1：When this IC is in the sleep-in state, the OLED driver power and boosting voltage
output are being shorted to the GND pin. Consequently, when taming on the
built-in power circuit, be sure to enter the sleep out command to cancel the
sleep-in state in advance.
2) Command entry procedures when turning off the power supply
Display OFF (CNTL[0]=”0”)
↓
Sleep-in (CTRL_PD=”1”) *2
↓
The power (VDDHV, VDD) will be shut down.
*2：In order to discharge the electric charge from the capacitor being connected to the
OLED drive power circuit, before shutting down the power, execute the sleep-in
command to bring the IC into the sleep state and wait until the OLED drive power
circuit output drops sufficiently before shutting down the VDDHV and VDD.
(Note)With this IC, the OLED output drive is being controlled by the logic circuits of
the power supply VDD-GND and VDDHV-GND. Therefore, if the power
supply VDD-GND and VDDHV-GND are shut down with some voltage still
remaining in the OLED drive power circuit output drops sufficiently before
shutting down the VDDHV and VDD.
3) Regarding the sleep-in/sleep-out sequence
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3.1)
Sleep-in sequence
Display OFF (CNTL[0]=”0”)
↓
Sleep-in (CTRL_PD=”1”)
3.2)
Sleep-out sequence
↓
<Power setting 1>
Sleep out (CTRL_PD=”0”)
↓
<Initial setting 1>
Initial control
Chip select signal (CS2=”1”)
Chip enable (CSB=”1”)
Read/write control (WTB=”1”)
↓
Oscillation ON
Internal Oscillator Clock Setting (not necessary, when use external oscillator)
8MHz：CNTL[4]=”1”,
4MHz：CNTL[4]=”0”.
↓
Oscillator Frequency (SETUP[5:4])
↓
Panel size setting
Control panel size (CNTL[7]=”1”)
↓
Set HPANEL (AA [2:0]=”000”)
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↓
Set VPANEL (AA [2:0]=”010”)
↓
Origin head-section setting (SETUP[7:6])
↓
Frame rate setting (CNTL[3])
↓
Contrast Control (SETUP[3:0])
↓
<Power setting 2>
Display ON (CNTL[0]=”1”)
↓
<Initial setting 2>
Brightness control (CNTL[2:1])
4) Refresh sequence
For recovering from miss-operation of IC, recommended to send commands, parameter
and display data periodically for refreshing data.
Following command and parameter
should be reset periodically.
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Sleep out (CTRL_PD=”0”)
Chip select signal (CS2=”1”)
Chip enable (CSB=”1”)
Read/write control (WTB=”1”)
Internal Oscillator Clock Setting (CNTL[4])
Oscillator Frequency (SETUP[5:4])
Control panel size (CNTL[7]=”1”)
Set HPANEL (AA [2:0]=”000”)
Set VPANEL (AA [2:0]=”010”)
Origin head-section setting (SETUP[7:6])
Frame rate setting (CNTL[3])
Contrast Control (SETUP[3:0])
Display ON (CNTL[0]=”1”)
Brightness control (CNTL[2:1])
During display, it might be happen that some noise at display is appeared. Re-setting
should be done during a display is off.
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8.0 Operation Modes
8.1 Edit Mode:
In EDIT mode, the performing of byte operations for graphics, use the following steps:
1) Select the desired Byte operation by writing to the OPCODE register
2) Write the VPOS register with the desired vertical position
3) Write the HPOS register with the desired horizontal position.
4) Write the DATA register with the desired data pattern. The actual byte write operation is
triggered by the DATA write cycle.
5) Subsequent byte operations require steps 2), 3) and 4) or only steps 3) and 4).
8.2 Video Mode:
In VIDEO mode, the performing pixel DATA write operations, use the following steps:
1) Set OPCODE [0, 0, 0] to start writing a video frame and to perform the selection of the
desired H1 and V1 pixel position.
2) Write the VPOS register with the desired V1 vertical position
3) Write the HPOS register with the desired H1 horizontal position.
4) Set OPCODE [0, 0, 1] to perform the selection of the desired H2 and V2 pixel position.
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5) Write the VPOS register with the desired V2 vertical position
6) Write the HPOS register with the desired H2 horizontal position.
7) Set OPCODE [0, 1, 0] to start the loading of video DATA by writing DATA bytes to each
pixel.
8) Write the DATA register with the desired gray scale data byte. The actual byte writing
operation is triggered by the DATA write cycle.
9) Subsequent pixel operations require steps 8, and the data placed in pixel sequence of
(H1,V1) – (H2,V1) – (H1, V1+1) – (H2, V1+1) -----(H1,V2) – (H2,V2).
10) Set OPCODE [0, 1, 1] to stop the loading of video DATA and frame.
11) If a subsequent video frame is to write, start the cycle from step (1) through step (10).
8.3 Controller Power Down Mode:
You can use CTRL_PD to set controller into power-down mode. When CTRL_PD is logic 1,
US2020 will enter Controller Power Down Mode. At this mode, the clock signal for controller will
be kept at logic 0, but internal register value is still the same. As to OEL panel, the OEL will be
anti-biased and not display anything until escaping from this mode. After leaving this mode, the
OEL will display pictures normally.
8.4 Driver Power Down Mode:
You can set CNTL [0] bit to logic 0 to disable charge pump circuit.
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9.0 Application Circuit
9.1 Using Internal Oscillator Application Circuit
OEL panel
136 x 160
DATA
1, 3, 5,…..157, 159
D
A
T
A
1
2
7
D
A
T
A
1
2
9
D
A
T
A
1
3
1
D
A
T
A
1
5
7
D
A
T
A
1
5
9
SS
CC
AA
NN
1 2
SCAN
DATA
1~136
2, 4, 6,…..158, 160
SS
CC
AA
NN
1 1
3 3
5 6
SCAN (1~136)
D
A
T
A
1
6
0
D
A
T
A
1
5
8
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D
A
T
A
1
3
2
DD
AA
TT
AA
1 1
3 2
0 8
US2020YA
DD
AA
TT
AA
1 1
2 2
5 3
D
A
T
A
3
D
A
T
A
1
V
D
D
H
V
G
N
D
H
V
G
NG
DN
HD
VH
1 V
C
T
D
RT
T
V
B
L E
E
D
DGC SC V I S W A A A U
HN S TS D P T T A A A S
VDB12 DD2 B 0 1 2 0
D
B
U
S
7
D
R
V
I
P
D
S
E
L
C
K
I
C
N
I R L
ESGOV
XT NCD
TBDK D
V
D
D
H
V
B
I
A
S
R
GE
NS
DP
HA
VD
G
NG
DN
HD
VH
1 V
V
D
D
H
V
DD
AA
TT
AA
2 4
D
A
T
A
1
2
4
D
A
T
A
1
2
6
R
Tr DC-DC
Vin
GND
Host Interface
18
IC
Vo
Vout (max. 18V)
VDD
Rev 1.01
2005/1/25
US2020
(Preliminary)
9.2 Using External Oscillator Application Circuit
OEL panel
136 x 160
DATA
1, 3, 5,…..157, 159
D
A
T
A
1
2
7
D
A
T
A
1
2
9
D
A
T
A
1
3
1
D
A
T
A
1
5
7
D
A
T
A
1
5
9
SS
CC
AA
NN
1 2
SCAN
DATA
1~136
2, 4, 6,…..158, 160
SS
CC
AA
NN
1 1
3 3
5 6
SCAN (1~136)
D
A
T
A
1
6
0
D
A
T
A
1
5
8
D
A
T
A
1
3
2
DD
AA
TT
AA
1 1
3 2
0 8
US2020YA
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DD
AA
TT
AA
1 1
2 2
5 3
D
A
T
A
3
D
A
T
A
1
V
D
D
H
V
G
N
D
H
V
G
NG
DN
HD
VH
1 V
C
T
D
RT
T
V
B
L E
E
D
DGC SC V I S W A A A U
HN S TS D P T T A A A S
VDB12 DD2 B 0 1 2 0
D
B
U
S
7
D
R
V
I
P
D
S
E
L
C
K
I
C
N
I R L
ESGOV
XT NCD
TBDK D
V
D
D
H
V
B
I
A
S
R
GE
NS
DP
HA
VD
G
NG
DN
HD
VH
1 V
V
D
D
H
V
DD
AA
TT
AA
2 4
D
A
T
A
1
2
4
D
A
T
A
1
2
6
External Clock
R
Tr DC-DC
Vin
GND
Host Interface
19
IC
Vo
Vout (max. 18V)
VDD
Rev 1.01
2005/1/25
(Preliminary)
US2020
10.0 Pad Assignment
D
A
T
A
1
2
7
394
D
A
T
A
1
2
9
D
A
T
A
1
3
1
D
A
T
A
1
5
7
D
A
T
A
1
5
9
S
C
A
N
1
3
5
SS
CC
AA
NN
1 2
3 3 3
9 9 9
3 2 1
S
C
A
N
1
3
6
D
A
T
A
1
6
0
D
A
T
A
1
5
8
D
A
T
A
1
3
2
DD
AA
TT
AA
1 1
3 2
0 8
2 2 2
2 2 2
6 5 4
SCAN (1~136)
223
Dummy Pads
Dummy Pads
Die Size = 11060 um x 4110 um
(INPUT / POWER /GND Pads)
454
1 1
6 6
1 2
1 2
DD
AA
TT
AA
1 1
2 2
5 3
D
A
T
A
3
D
A
T
A
1
D
A
T
A
1
2
4
DD
AA
TT
AA
2 4
163
D
A
T
A
1
2
6
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